These circuits are necessary notably in applications where the power supply is provided by a battery or a cell (portable telephones, cameras, portable computers, etc.), so as not to needlessly consume the energy of the power supply source.
In these applications, the circuits are generally made by CMOS technology (complementary metal oxide semiconductor), allowing lower consumption than other technologies.
To switch from an active mode to a standby mode, a power transistor TP interposed in series between one of the supply terminals A or M of the integrated circuit and the active part of the circuit (CA) is generally envisaged in the integrated circuit, as seen in FIG. 1; this transistor is controlled by a mode management circuit CGM which establishes one voltage or another on the gate of the transistor depending on whether the integrated circuit is in the active mode or on standby; the function of this power transistor is twofold:                in active mode: it is rendered highly conducting and allows through the whole of the current necessary for the active circuit, with a minimum voltage drop, therefore without needless power consumption;        in standby mode: it is off so as to interrupt the current from the power supply source to the remainder of the integrated circuit.        
The power transistor must therefore meet several constraints: sufficiently high current in the on state; very low voltage drop in the on state; very low leakage currents in the off state; and finally, if possible, dimensions that are as reduced as possible so as to reduce the space required on the silicon of the integrated circuit.
Various types of power transistors attempting to meet this set of constraints have already been proposed in the prior art. Examples thereof will be found notably in the following published documents:
S. Mutoh et al., “1-V Power Supply High Speed Digital Circuit Technology with Multithreshold-voltage CMOS”, IEEE Journal of Solid State Circuits, vol. 30, pp 847-854, August. 1995.
T. Inukai et al., “Boosted Gate OS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration”, Custom Integrated Circuits Conference, pp. 409-412, May 2000.
H. Kawaguchi et al., “A super Cut-Off CMOS (SCCMOS) Scheme for 0.5 V Supply Voltage with Picoampere Stand-by Current”, IEEE Journal of Solid State Circuits, vol. 35 No. 10, pp 1498-1501, October 2000.
In the latter document, use is made of a power transistor with low threshold voltage providing a high current in the on state and whose leakage current is reduced by reverse over-biasing the gate in standby mode; by reverse overbias is understood a bias at a voltage lower than the most negative terminal of the supply voltage, for an NMOS transistor, or higher than the most positive supply voltage for a PMOS transistor.
The power transistor of the document cited last is that which exhibits the best compromise between area occupied (for a given current in the on state), and leakage current in the off state.
It is noted that the leakage current, which is firstly due to the conduction current ISTH between source and drain (sub threshold current) decreases exponentially when the gate is biased more negatively (for an NMOS); it can become extremely low. However, a second phenomenon must be taken into account; this involves the appearance of a drain current induced by the gate: by reverse biasing the gate, a leakage current no longer appears between drain and source but between drain and substrate of the integrated circuit. Typically, in the configuration of FIG. 1 where the power transistor TP is a PMOS transistor whose source is linked to the most positive supply terminal A, the gate is brought to a still more positive potential in standby mode, while the drain will remain practically at the potential of the terminal M which is the low potential of the power supply. The electron-hole pairs generated naturally in the drain experience the influence of the sizeable electric field which then exists between gate and drain just where the gate overhangs the edge of the drain; the electric field generated between gate and drain tends to locally lower the potential barrier between drain and substrate; electrons can cross this barrier and pass towards the substrate, creating a substrate/drain leakage current despite the interruption of the source/drain current. This current IGIDL or drain current induced by the gate increases significantly when the voltage between gate and drain increases; the increase is substantially exponential.
The gate reverse overbias therefore gives rise to an additional leakage current for the power supply battery of the circuit, and this current grows strongly with the overbias level. This implies that if the gate-source voltage is increased too much negatively (NMOS) or positively (PMOS), the very strong reduction in the leakage current between source and drain no longer serves any purpose since another source of leakages becomes predominant.
The curve of FIG. 2 represents an exemplary plot of the two curves of leakage current varying in opposite directions. The scale is logarithmic for the currents along the ordinate and linear for the gate-source voltages along the abscissa. As long dashes the conduction current between drain and source ISTH; as short dashes: the drain current induced by the gate IGIDL (short dashes); as a solid line, the sum of these two currents which is the total leakage current IOFF. The curve is plotted for an NMOS transistor, the gate-source voltage having negative values (gate more negative than the source); for a PMOS transistor, the curve would be identical but graduated as positive voltage (gate more positive than the source).
It is seen that the total leakage current exhibits a minimum for a certain gate-source voltage value, and it would be optimal to be at this value in standby mode.
Unfortunately, this optimal point is not easy to find in reality because of the spread in the technological parameters, within a fabrication or between several fabricated batches. It depends also on the value of the supply voltage of the circuit and the temperature. FIG. 3 illustrates an exemplary variation as a function of temperature; the curves of leakage current IOFF plotted in this figure, for respective temperatures of −40° C., −25° C., 0° C., +25° C., +50° C., +100° C., +125° C., show that the current can vary by more than a decade and a half between −40° C. and +125° C. when one is at the minimum of the curve at +25° C., and still more if one is to the right of the minimum.
In the prior art, it has been proposed to compare the leakage currents of two transistors similar to the power transistor but smaller and biased at two different gate voltages but such that their leakage currents are equal, and to then bias the power transistor at an intermediate value between the two different voltages, this value representing nearly the optimum.
This is described in patent publication WO 2006/017082 A2.
This document also describes another procedure using a single transistor similar to the power transistor; the leakage current is measured by the discharge time of a capacitor precharged to the supply voltage; one seeks the bias which maximizes the discharge time. But the discharge time might vary over a very wide span of values, and, moreover, the control transistor will not be under the same supply voltage conditions in the course of the discharge as the power transistor, thereby corrupting the principle of the measurement.
There also exists a third procedure, described in the article by C. Neau et al., “Optimal Body Bias Selection for Leakage Improvement and Process Compensation Over Different Technology Generations”, ISLPED, 2003. This procedure is applicable to certain types of transistors only; it consists in reverse biasing the semiconductor substrate on which the power transistor is formed. But this procedure makes it necessary to find a compromise between two opposite currents whose variation is opposite as a function of bias, which are respectively the band-to-band tunnel current (IBTBT) and the subthreshold conduction current ISHT.